As a quick follow up to the previous post on the working of the solar cell let me just point out that for the piece of semiconductor to act as a solar cell three conditions must be met ^* : (i) semiconductor must feature energy gap (E_g) narrow enough so that it will absorb as much as possible of the impinging solar light, (ii) a potential barrier must be created somewhere within its body so that photogenerated electrons and holes will get separated by the electric field associated with a barrier, and (iii) ohmic contacts must be formed at the two sides of the potential barrier so that electric charges can flow freely in and out of the device.

And that's the "working" part of the solar cell story. The rest of it is engineering.... and money.

* The rules are somewhat different in the case of solar cells manufactured using organic     semiconductors.

 In the current solar cell frenzy little attention is being paid to what actually makes semiconductor solar cell work. Specifically, what are the reasons why the illumination of the piece of semiconductor equipped with two terminals generates a difference of potential (voltage) at these two terminals (open circuit voltage).

There is so much going on in semiconductor science and engineering these days and semiconductor technology is becoming such a diversified technical domain that grasping the entire breadth of it is does not seem to be possible.  On the surface organic LEDs on flexible substrates and 45 nm terahertz CMOS circuitry, MEMS actuators and quantum nanodot devices, power MOSFETs and III-V superlattices, do not have much in common.  

Such a segmentation of thinking about semiconductor science and technology should not be allowed into the  teaching of semiconductors at the undergraduate level. Isn’t it that the principles of the field effect are the same in advanced Si CMOS gates, organic TFTs, power UMOSFETs, nanowire transistors, and so on? The concept of carrier mobility cuts across all semiconductor materials and devices? Fundamentals of the ohmic contact are the same regardless of the function of the device and semiconductor used? And it's regardless of whether “micro” or “nano” is the prefix of the day? The principles of key processing steps such as pattern definition or film deposition via CVD, PVD, ALD, etc., are independent of the type of device and material?  Or,… well, you’ve got the point…

I strongly believe that it is very important that while teaching semiconductors we emphasize those commonalities, we stress fundamentals, and do not paint a picture in which processing of 32 nm Si CMOS circuitry and Si solar cells, for instance, have nothing in common and represents two entirely different technical domains. Keeping in mind fundamentals we will end up educating future engineers and scientists who will be able to see a proverbial "big picture". No real breakthroughs can be accomplished without it.

Our ability to process and transmit an information is all dependent upon devices and information carrying medium which can be turned "on" and "off" fast enough so that corresponding sequence of "1"s and "0"s can be executed billions of times per second. The search for this perfect switch goes on forever and is among key forces driving  our progress.

The good news for us, semiconductor buffs, is that for the last fifty years, or so, it is based entirely on the advances in semiconductor technology. For now, it is a flow of electrons and a CMOS cell.... But the need to transmit an information  was always there.  Not  that long ago it was a smoke and  the blanket operated by a skillful warrier. Then, the electric current turned on and off according to the Morse code, etc., etc. What will it be in the future? Well, that's what we are trying to figure out. The good news one more time: whatever media and devices we will come up with, we can rest assured that semiconductors will be somehow invloved.

More on the tunneling, this time in the upbeat tone. As both horizontal and vertical geometries of semiconductor devices continue to shrink and the demand regarding device functionality increases, the role of quantum tunneling in the next generation semiconductor devices can only grow. This is very this very important conduction mechanism is getting our very serious attention now. 

The tunneling is a very important physical phenomenon – it allows a charge carrier to move across the potential barrier without changing energy. It is an "elegant" physical phenomenon, if I may use such a non-scientific terminology.  And a clear cut one - the potential barrier is adequately narrow, tunneling will occur; the barrier gets wider, probability of direct tunneling goes down exponentially.

Several semiconductor devices displaying unique electronic properties, including those based on quantum wells, as well as various memory devices, involve electron tunneling effect.  Yet, in recent years, in cutting edge CMOS technology, tunneling is getting a bad name and is considered a highly undesirable, parasitic effect. This is because the physical thickness of the gate oxide (SiO₂) in the most advanced MOS gates ended up being reduced to the limit of about 1 nm. At such a negligible width of the potential barrier the direct tunneling of electrons across the gate oxide is the main reason for an excessive leakage current which ruins the performance of the MOS gate stacks.

Continuing on the topic of materials in IC technology the case of silicides is an interesting one. This is because transition from one type of silicide to another takes place relatively fast by semiconductor industry standards. Not long ago is was titanium silicide, TiSi2, then cobalt silicide, CoSi2, then nickle silicide NiSi (see the comparison between these three). Now we are talking NiSi with Pt added and in the near future erbium and iridium silicides for instance may take over as lead silicides for ohmic contacts.
 
Well, things are relatively easy when improvement can be accomplished by replacing just one element in the otherwise established process.

Any replacement of one material with another in mass IC production is a very costly and a very disruptive process. Hence, any such step is delayed as much as possible and is implemented only if no other solution assuring an improvement in circuit performance is available. For instance, it was not until interconnect technology was push hard against the red wall that the switch from Al to Cu was reluctantly implemented. The same applies to the recently announced switch in MOS gate technology from SiO2-based to high-k gate dielectrics.

One of the reason I enjoy ECS meetings is a diversity of topics covered by some thirty or so symposia held during the four days long gatherings. While focusing on one or two "semiconductor symposia" I always find time to check on what's going on in the research areas to which I normally don't have much of an exposure. It's kind of fun to wonder into the room and listedn to the talk on electrochemical biosensors or fullerenes and carbon nanotubes or biological fuel cells or.....

By the way, the next ECS meeting will take place in mid-October 2008 in Honolulu, Hawaii. There will be 15 semiconductor related symposia held during this particular meeting. If interested in submitting an abstract you must hurry as the deadline for the abstract submission is May. 30.

Greetings from Phoenix, Arizona. That's where the 213th biannual meeting of the Electrochemical Society is taking place. The ECS, defining itself as the Society for Solid-State and Electrochemical Science and Technology, was born in 1902 and continues to be among the prime science and technology related societies in the world. I am a member of ECS for over 20 years and, because of the traditionally very strong semiconductor component in the ECS's fabric, I draw much from this association.

Just to get a feel for what's going on during the ECS meeting in Phoenix you may want to take a look at the today's plenary session talks as well as at the semiconductor related symposia held during this meeting.