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Tuesday, November 18, 2008
Wafer thickness – a new paradigm
The diameter of single-crystal silicon wafers used in IC manufacturing continue to increase from 50 mm or so in the early years to 450 mm planned for few years from now. A gradual increase of the wafer thickness had to follow to assure adequate mechanical stability of still larger wafers. For the largest wafers, thickness approaching
1000 micrometer (1 mm) will be required to make sure that they are sturdy enough to be safely handled by fully automated process tools. Additional reason is that in order to prevent serious malfunctions of the lithographic patter transfer processes their flatness cannot be altered in any way during handling.
What is in a way paradoxical is that as the wafers are getting thicker their portion into which devices are being built is getting thinner (a requirement of the scaling rules). It means that more and more of high quality silicon is used for nothing more than the
mechanical support of the circuitry formed on its surface.
The exactly opposite trend emerges in crystalline Si solar cell technology. Here, the wafer must be as thin as possible to cut on the cost of the solar panels which require very large volumes of silicon. As a result, what has moved these days to the forefront of solar cell engineering is a technology of slicing multicrystalline Si ingots into wafers which eventually will have to be as thin as 40 μm. In the case you don’t sense what it means: at this thickness Si wafers hardly maintain their mechanical cohesiveness. Hence, their handling, processing, etc. will require technical solutions which are not in place yet. Posted by Jerzy Ruzyllo at 09:11 PM |
Semiconductors
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Wednesday, November 12, 2008
A word about engineering graduate programs rankings
For a change, this time not about semiconductors…..
Academic community, administrators as well as faculty closely follow rankings of universities and various academic programs. Recently, I came across and took a closer look at the US News and World Report 2008 rankings of engineering graduate schools. I also looked at the criteria applied in the ranking process and noticed that it is based more on the perception and to the lesser extent on the tangibles. Personally, I think that the current balance between various criteria used would benfit from tilting it somewhat toward the latter.
I happened to believe that the performance of the respective Ph.D. programs should be an important element in the evaluation of engineering graduate programs in general. This is because the process of achieving a Ph.D. degree epitomizes graduate education. This is where teaching/mentoring, research and external funding must come together to create a "product". Hence, the Ph.D. output of the program reflects its balance and overall strengths.
The shear number of Ph.D. degrees granted in any given year is not a right measure because it depends on the graduate enrollment which not necessarily is a represenation of the quality of the graduate program. However, a percentage of the total enrollment representing students graduating with a Ph.D. degree in any given year could be used as a measure of the efficiency of the graduate program and the role of its Ph.D. component.
Applying this criterion and using data for the first 25 engineering graduate programs in the US News and World Report ranking for the year 2008 it turns out that Cal Tech came on top of the pack in terms of the Ph.D. output. In 2008, 20.89% of the total number of students in the engineering graduate program at Cal Tech (536) graduated with a Ph.D. degree (112 students). Princeton (16.95%), Harvard (13.23%), UC Santa Barbara (13.12%), UC Berkley (12.52%) and MIT (12.44%) followed.
I agree, this is just one way of looking at the process of ranking engineering graduate programs. To me, however, with just one number it tells much about the strengths and the profile of such program. Posted by Jerzy Ruzyllo at 07:50 PM |
Semiconductors
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Thursday, November 6, 2008
A full circle
The very first research project I was working on many, many, years ago (fresh out of school and before Ph.D.) involved studies of ohmic contacts to thin-film cadmium selenide, CdSe. At that time CdSe was considered mainly for its potential in IR (infrared) photonics. Soon, however, I switched my research interests to silicon and never thought I would be involved with CdSe again.
It turns out that I was wrong as recently, some thirty years later, one of my research projects is once again focused on CdSe. This time, however, it is because of quantum confinement properties of CdSe making it attractive in nanocrystalline quantum dots LEDs, and eventually, displays applications.
Conclusion: you never know...... Thirty years ago the concept of quantum confinement was strictly theoretical.
Posted by Jerzy Ruzyllo at 08:04 PM |
Semiconductors
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Saturday, November 1, 2008
Trends in cleaning technology
Following up on my October 9th blog on UCPSS 2008……
The most recent UCPSS (Ultra Clean Processing of Semiconductor Surfaces) symposium was helpful in identifying trends in the R&D of surface cleaning/preparation technology. Here are few of them that I’ve noticed:
* Germanium is an object of increased attention in the semiconductor cleaning community. Hence, as I mentioned earlier, silicon is no longer its sole focus (see “Reemergence of germanium” entry of March 17, 2008). As cleaning chemistries in these two cases are not the same the field of Ge cleaning technology is open for exploration. The same applies to III-V cleaning where the demand for the effective cleaning solutions is growing.
* All of the above is driven by the emerging needs of the next generation ultra-low power, ultra-high speed logic IC.
* As the device active areas (and films in general) are getting thinner and geometries tighter the need to prevent material loses and surface damage during cleaning operations is getting increasingly critical.
* Due to the fragility of ultra-small geometrical features created these days on processed surfaces the possibility of pattern collapse during aggressive wet cleaning and rinsing operations is of significant concern.
* The concern mentioned above is a reason for the renewed interest in HF vapor, or anhydrous HF (AHF), with addition of the vapor of an alcoholic solvent (e.g. methanol or ethanol) in various oxide etching applications (see “Anhydrous HF” entry of March 30, 2008). This technique is coming very handy in MEMS release operations and can be very useful in native/chemical oxide removal from the very fragile surface features.
* An interesting trend is an attempt to use straight water in the form of aerosol spray, or high-speed steam water mixed spray for nanoparticle removal.
* An aggressive push toward even more dilute cleaning chemistries continues (a result of the need to reduce surface damage and material losses). A precise control over the pH of cleaning chemistries is a guiding light in this process.
Listed above are just examples of noticable trends. Overall, semiconductor cleaning technology is challanged now as much as it was ever in the past. Just the nature of challanges changes with time. Posted by Jerzy Ruzyllo at 07:15 PM |
Semiconductors
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Wednesday, October 22, 2008
ECS Fall meeting – a comment about TFT technology
The technology of semiconductor devices and circuits formed on the flexible substrates, i.e. on easily bendable, typically transparent sheets of various polymeric materials, is maturing rapidly. The interest is driven mainly by the appeal of the flexible displays but not only. Electronic and photonic systems on fabrics, paper, etc., will certainly find many applications, including those which we don’t even foresee at this time.
At the core of almost any such system there is a Thin Film Transistor, TFT. Hence, the progress in TFT technology on flexible substrates is a good measure of the progress in flexible electronics and photonics in general. As the recent ECS Fall meeting indicates, the advancements in flexible TFT technology, whether using amorphous Si, organic semiconductor or ZnO for instance, are quite impressive. In nowadays semiconductor science and engineering it is certainly a domain which should be followed closely. Posted by Jerzy Ruzyllo at 08:18 PM |
Semiconductors
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Tuesday, October 14, 2008
A day at the ECS meeting
What I like about ECS meetings is the diversity of topics you can get exposed to if you will take time to walk the hallways and sneak into a variety of sessions underway. Just to give you an example, during one day I did:
- listened to the colorful talk by Paul Agnello of IBM stressing the concept of “no strain, no gain” going from 90 nm to 45 nm technology node (very little scaling at this stage) and “the pain of strain” for below 45 nm (with an introduction of high-k gate dielectrics, etc., scaling is back) and stating that until atomic limits of gate length at about 10 nm the CMOS will do just fine;
- caught up with an issue of heat management in cutting edge CMOS on SOI substrates (overheating will eliminate part of the gains in terms of the increased mobilty resulting from the strained channel);
- brought myself up to speed with regard to GaAs surface preparation in the processing of GaAs MOSFETs with high-k gate dielectrics;
- learned about problems with creating a network comprised of carbon nanotubes (and graphene for that matter) where resistance of contact between tubes alleviates to a significant degree the benefits of the very high conductivity of an individual tube;
- listened to the number of presentations devoted to ZnO based thin films, nanowires and nanobelts (see the blog of July 29);
- brushed up on the issues related to Si epitaxial and solar cell substrates;
- got a feel for what biophotonics is all about;
- got a sense of direction in the ALD related research
And it all without even mentioning a very heavily attended symposium on “SiGe, Ge, and Related Compounds: Materials, Processing and Devices” during which a countless number of meaningful papers are being presented.
In short, a real El Dorado for somebody interested in state-of-the-art semiconductor science and engineering.... Posted by Jerzy Ruzyllo at 10:51 PM |
Semiconductors
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Sunday, October 12, 2008
ECS meeting in Honolulu
Every few years the Electrochemical Society (ECS) holds its meeting jointly with the Electrochemical Society of Japan. A gathering place on such an occassion is typically Honolulu, Hawai. The next meeting in the series is starting today (October 12-17,2008).
For those of you who are not immediately familiar with ECS - ECS is an electrochemical and solid-state science society with a very strong semiconductor component. For instance, in the program of the current meeting there are 14 symposia directly related to semicondcutor science and engineering. You will find a complete listing on www.electrochem.org but let me assure you that any "semiconductorer" will find something of interest in this meeting's semiconductor menu. Posted by Jerzy Ruzyllo at 02:43 PM |
Semiconductors
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Thursday, October 9, 2008
UCPSS 2008
The International Symposium on Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing organized under the auspices of the Electrochemical Society (watch for the next one in October 2009 in Vienna, Austria) and International Symposium of Ultra-Clean Processing of Semiconductor Surfaces (UCPSS) organized by IMEC in Belgium are the two lead symposia in the broadly understood area of semiconductor cleaning and surface conditioning.
The 2008 version of UCPSS was held two weeks ago in Bruges, Belgium. Few comments and observations
- silicon is no longer a sole focal point in semiconductor cleaning R&D; germanium, SiGe, as well as III-V semiconductors are increasingly visible on the radar screen of semiconductor cleaning community
- FEOL (Front-End-of-the- Line) surface preparation is going strong, although, number of BEOL (Back-End-of-the-Line) cleaning related contributions increases from symposium to symposium.
more to come shortly..... Posted by Jerzy Ruzyllo at 08:33 PM |
Semiconductors
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Saturday, October 4, 2008
Contaminants
A quick reminder that while the technology progresses and new semiconductor materials and device structures are being introduced, the problem of contamination of process ambient, process equipment, gases, water, etc. is as valid and as potentially damaging as ever. And the key types of contaminants in semiconductor fabrication environment we have to worry about remain the same...... Posted by Jerzy Ruzyllo at 07:57 PM |
Semiconductors
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Saturday, September 6, 2008
Organics vs. nanodots
On Aug. 17 I posted a comment with regard to the apparent "competition" between crystalline silicon wafers and amorphous* Si thin films for the share of the solar cells market. Later on I realized that there other "competiotions" of this nature in semiconductor technology. One that came to mind is a choice between organic semicondictors and semiconductor quantum dots in realizing next generation LEDs, and then displays. Both are compatible with flexibe display technology which (flexibility) is currently among the most important topics in dispaly science and engineering. At present, organics seems to have an edge, but things may change when manufacturability, cost, realibility, etc. etc. factors will come to play.
* for those who may not know - term "amorphous" simply means noncrystalline, i.e. a material in which atoms are distributed not following any specific long range order. Posted by Jerzy Ruzyllo at 07:52 PM |
Semiconductors
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